1. Field of the Invention
Generally, the present invention relates to the fabrication of integrated circuits, and, more particularly, to the formation of stabilized metal silicide regions in transistor elements containing silicon-germanium material.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features have been steadily decreasing in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. However, commensurate with the on-going shrinkage of feature sizes, certain size-related problems arise that may at least partially offset the advantages that may be obtained by simple size reduction alone. Generally speaking, decreasing the size of, for instance, circuit elements such as MOS transistors and the like, may lead to superior performance characteristics due to a decreased channel length of the transistor element, thereby resulting in higher drive current capabilities and enhanced switching speeds. Upon decreasing the channel length of transistor elements, however, the electrical resistance of conductive lines and contact regions—e.g., those regions that provide electrical contact to the transistor elements—becomes a significant issue in the overall transistor design, since the cross-sectional area of these lines and regions is similarly decreased. However, the cross-sectional area of the conductive lines and contact regions, together with the characteristics of the materials they comprise, may have a significant influence on the effective electrical resistance of these circuit elements.
Furthermore, as integrated circuits become smaller and more closely spaced—i.e., as the number of circuit elements that are packed within a given unit area of a semiconductor device substrate increases—greater the number of interconnections that are required between these circuit elements. Moreover, it is not uncommon for the number of required interconnects to increase in a non-linear fashion relative to the number of circuit elements, such that the amount of “real estate” available for interconnects becomes even further limited, thus increasing the likelihood that the cross-sectional area of critical conductive elements might be further reduced.
Presently, the majority of integrated circuits are silicon-based, that is, most of the circuit elements comprise silicon-containing regions which act as conductive areas. These silicon-containing regions may be in crystalline, polycrystalline and/or amorphous form, and they may be doped and/or undoped, as may be required for the specific conductivity of the specific circuit element. One illustrative example in this context is that of a gate electrode of a MOS transistor element, which may be considered as a polysilicon line. Upon application of an appropriate control voltage to the gate electrode, a conductive channel is formed proximate the interface of a thin gate insulation layer and an active area of the semiconducting substrate. Although the design step of reducing the feature size of a transistor element tends to improve device performance, due to the reduced channel length, the commensurate shrinking of the gate electrode may otherwise result in significant delays in the propagation of the signal along the channel width direction. Moreover, the issue of signal propagation delay is further exacerbated for polysilicon lines connecting to individual circuit elements or to different active areas within the device. Therefore, it is particularly important to improve the sheet resistance of polysilicon lines and other silicon-containing contact regions so as to allow further device scaling without compromising overall device performance. For this reason, and depending upon the device design requirements, it has become commonplace to reduce the sheet resistance of polysilicon lines and silicon contact regions by forming a metal silicide in and on appropriate portions of the respective silicon-containing regions.
With reference to FIGS. 1a-1e, one illustrative prior art process flow for forming a metal silicide on a corresponding portion of a representative MOS transistor element will now be described.
FIG. 1a schematically shows a cross-sectional view of an illustrative semiconductor device 100 comprising a substrate 101, in and above which an illustrative MOS transistor element 150 may be formed based on well-established semiconductor device processing techniques. The substrate 101 may represent any appropriate substrate on which may be formed a semiconductor layer 103, such as a silicon-based layer, or any other appropriate semiconductor material that facilitates the formation of the transistor element 150. It should be appreciated that the semiconductor layer 103, even if provided as a silicon-based layer, may include other materials, such as germanium, carbon and the like, in addition to an appropriate dopant species for establishing the requisite conductivity type in an active area 102 of the semiconductor layer 103. Furthermore, in some illustrative embodiments, the transistor element 150 may be formed as one of a plurality of bulk transistors, i.e., the semiconductor layer 103 may be formed on or be part of a substantially crystalline substrate material, while in other cases specific regions of the device 100, or the entire device 100, may be formed on the basis of a silicon-on-insulator (SOI) architecture, in which a buried insulating layer (not shown) may be provided below the semiconductor layer 103.
As shown in FIG. 1a, the transistor element 150 includes a gate electrode structure 120 formed above an active area 102. The active area 102 may be enclosed by an isolation structure 104, which in the present example is provided in the form of a shallow trench isolation, as may typically be used for sophisticated integrated circuits. In the illustrated embodiment, highly doped source and drain regions 106 are formed in the active area 102, along with source/drain extension regions 105 that usually comprise a dopant concentration less than that of the highly doped regions 106. The source and drain regions 106, including the extension regions 105, are laterally separated by a channel region 107. Also as shown in FIG. 1a, the gate electrode structure 120 may include a gate insulation layer 108 formed above the channel region 107, which electrically and physically isolates a gate electrode 109 from the underlying channel region 107, as well as sidewall spacer structures 110 formed adjacent to the sidewalls of the gate electrode 109.
The gate electrode structure 120 may be one of several configurations well known in the art, such as a conventional gate oxide/polysilicon gate electrode (polySiON) configuration, or a high-k dielectric/metal gate electrode (HK/MG) configuration. When a conventional polySiON configuration is contemplated, the gate insulation layer 108 may comprise a conventional gate dielectric material, such as, for example, silicon dioxide, silicon oxynitride, and the like, and the gate electrode 109 may comprise polysilicon. On the other hand, when an HK/MG configuration is used, the gate insulation layer may be one of several well-known high-k gate dielectric materials (i.e., materials having a dielectric constant “k” greater than 10), such as tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO2) and the like, whereas metal gate stack comprising, for example, metal gate materials such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium silicon nitride (TiSiN) and the like, may be used for the gate electrode 109. Furthermore, the upper portion of the metal gate stack of an HK/MG configuration may also comprise polysilicon. Other materials and combinations may also be used.
Depending on the device requirements and/or the overall processing strategy, the sidewall spacer structures 110 may comprise one or more suitable dielectric materials, such as silicon nitride, silicon dioxide, silicon oxynitride, and the like. Furthermore, the sidewall spacer structures 110 may include two or even more spacer elements, such as offset spacers, conformal liners, and the like, which may act as appropriate implantation masks for creating the lateral dopant profile for the highly doped drain and source regions 106 and extension regions 105. The configuration shown in FIG. 1a depicts the illustrative semiconductor device 100 after dopants in the drain and source regions 106 and the extension regions 105 have been put on substitutional lattice sites by an activation annealing step.
It should be appreciated that when the transistor element 150 represents a PMOS transistor, device performance can sometimes be enhanced by inducing a compressive stress in the channel region 107 of the transistor element 150 so as to increase hole mobility. In some cases, a compressive stress may be induced in the channel region 107 by forming “embedded” stressed material regions 103a in the upper portion of the source and drain regions 106 and on either side of the channel region 107, thus leading to improvements in the overall speed and performance of the PMOS transistor element 150. In some PMOS transistor elements, the stressed material regions 103a may be created by forming cavities 103c in the active area 102 on either side of the gate electrode structure 120. Thereafter a silicon-germanium material layer may be epitaxially grown so as to completely fill, or even over-fill, the cavities 103c, thus forming embedded material regions 103a. As is known to those having skill in the art, the epitaxially grown silicon-germanium material may take on a lattice structure and crystal orientation that is substantially identical to those of the silicon material comprising the active area 102 of the semiconductor layer 103. Furthermore, since the molecules comprising a silicon-germanium material are larger than those comprising a material that is substantially silicon (as may comprise the semiconductor layer 103), the larger silicon-germanium atoms may induce a localized compressive stress on the surrounding smaller atoms of the substantially silicon material in the active area 102 of the semiconductor layer 103, thereby causing a compressive stress on the channel region 107 of the PMOS transistor element 150. After forming the silicon-germanium material regions 103a, the sidewall spacer structures 110 may be formed and dopants may be implanted in the active area 102 so as to form the extension regions 105 and deep drain and source regions 106, followed by an activation anneal as previously discussed.
FIG. 1b schematically depicts the semiconductor device 100 of FIG. 1a after a refractory metal layer 111 is formed on the transistor element 150. Depending on the overall device processing strategy, the refractory metal layer 111 may be formed using a suitable material deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like, and may comprise any one of a number of refractory that are used to form metal silicide contacts in the gate electrode and source/drain regions of transistor elements metals, as are well known in the art, such as nickel, titanium, cobalt, and the like. While the type of metal silicides used for a given contact region may depend on specific device requirements, nickel silicide provides some distinct advantages over cobalt and titanium silicides. For example, nickel monosilicide contacts are typically thinner than the conventional titanium or cobalt disilicide contacts, therefore less silicon base material is consumed during the silicide conversion process. Moreover, lower heat treating temperatures are typically used for forming nickel monosilicide as compared to forming cobalt or titanium disilicides, thereby necessitating a lower overall thermal budget. Therefore, for highly sophisticated transistor elements, nickel is increasingly considered as an appropriate substitute for both cobalt and titanium. Accordingly, it is therefore assumed in the following description that the refractory metal layer 111 is substantially comprised of nickel. In some embodiments, the refractory metal layer may also comprise platinum, which in some cases may promote a more homogeneous formation of nickel monosilicide.
After deposition of the refractory metal layer 111, a heat treatment process 121 may be performed so as to initiate a chemical reaction between the nickel atoms in the layer 111 and the silicon atoms in those areas of the source and drain regions 106 and the gate electrode 109 that are in contact with the nickel, thereby forming nickel silicide regions that substantially comprises low-resistivity nickel monosilicide. The heat treatment process 121 is generally a two-step process, wherein a first heat treatment step is performed in the range of approximately 300°-400° C. for a time period of approximately 30-90 seconds to primarily form nickel monosilicide, with some isolated regions of higher resistivity nickel disilicide also being present. After the first heat treatment step, any non-reacted nickel material from the refractory metal layer 111 is selectively removed by an etch/cleaning process, of which suitable recipes are well known in the art. Furthermore, in those instance where the refractory metal layer 111 also comprises platinum to facilitate silicide formation, the etch/cleaning process may include a second etch step based on, for example, aqua regia, to remove any residual platinum metal remaining on the exposed surfaces of transistor 150. Thereafter, a second heat treatment step is performed in the range of approximately 400°-500° C., again for a time period of approximately 30-90 seconds, to convert the regions of higher resistivity nickel disilicide into regions of low-resistivity nickel monosilicide. It should be noted that the silicon material contained in the sidewall spacer structures 110 and the shallow trench isolation regions 104 does not substantially take part in the chemical reaction induced during the heat treatment process 121, as it is present in those features only as a thermally stable silicon dioxide and/or silicon nitride material.
FIG. 1c schematically shows the semiconductor device 100 after the two-step heat treatment process 121 has been completed and the unreacted portions of the refractory metal layer 111 have been removed from above the transistor element 150. As illustrated in FIG. 1c, nickel silicide layers 112 have been formed in the contact region 112c at the upper surface of the source and drain regions 106, and nickel silicide layer 113 has been formed in the contact region 113c at the upper surface of the gate electrode 109. Furthermore, in the processing stage illustrated in FIG. 1c, a stressed material layer 114, having, for example, an inherent tensile stress, is formed above the semiconductor device 100 so as to enhance the performance of the transistor element 150. The stressed material layer 114 may comprise a dielectric material having an etch selectivity to an interlayer dielectric material layer 115 formed above the semiconductor device 100 during a later manufacturing stage (see, e.g., FIG. 1e). For example, the stressed material layer 114 may be a silicon nitride layer, which may be formed above the transistor element 150 using a suitably designed deposition process 122, such as a plasma-enhanced chemical vapor deposition (PECVD) process, and the like. Furthermore, the process recipe of the deposition process 122 may be adjusted as required so that the tensile stress of the as-deposited silicon nitride stressed material layer 114 is in the range of approximately 800-1200 MPa. For example, the deposition process 122 may be performed under a pressure that is in the range of 300-1200 mTorr, at a temperature between 400°-500° C.
FIG. 1d schematically illustrates the semiconductor device 100 shown in FIG. 1c in a further manufacturing stage, wherein the stressed material layer 114 is exposed to an ultraviolet light (UV) cure 123. The UV cure 123 is performed in the range of 400°-500° C., and is performed so as to increase the tensile stress of the silicon nitride stressed material layer 114 to a level greater than 1 GPa, up to as high as 2 GPa, thereby further enhancing the overall speed and performance of the transistor element 150.
As previously noted, when the transistor element 150 represents a PMOS transistor, a silicon-germanium material region 103a may be embedded in the upper portion of the drain and source regions 106 so as to induce a compressive stress in the channel region 107, thereby facilitating hole mobility and increasing device performance. However, in PMOS transistors having silicon-germanium material in the drain and source regions 106, the nickel silicide material 112 present in contact regions 112c tends to agglomerate, or cluster, under exposure to the UV cure 123, into agglomerated nickel silicide regions 112a, as schematically depicted in FIG. 1d. By contrast, nickel silicide agglomeration does not occur under exposure to the UV cure 123 in the nickel silicide layer 113 in the upper portion of the gate electrode 109, which is comprised substantially of polysilicon material. Accordingly, it is believed that nickel silicide agglomeration may possibly be caused by the presence of germanium, which may tend to “destabilize” the microstructure under exposure to UV light, thereby allowing some degree of nickel silicide and/or silicon-germanium material diffusion to occur. Moreover, it is also believed that the greater the concentration of germanium, the more “unstable” the microstructure may become. For example, the rate of material diffusion and subsequent agglomeration of nickel silicides formed in silicon-germanium materials and exposed to UV light appears to be worse in alloys having a germanium concentration of 35% by weight, as compared to a germanium concentration of 20% by weight. As depicted in FIG. 1d, this material diffusion under the UV cure 123 can lead to the spotty presence of agglomerated nickel silicide regions 112a in the contact regions 112c, which may potentially cause product defects and thereby result in reduced product yield, as will be discussed below.
After the UV cure step 123 has been completed, an interlayer dielectric material layer 115 may be formed above the semiconductor device 100, as illustrated in FIG. 1e. Thereafter, an anisotropic etch process 124, such as a reactive ion etch (RIE) process and the like, may be performed on the basis of an appropriately patterned etch mask layer 116 so as to form via openings 117 and 118 in the interlayer dielectric material layer 115. Depending on etch selectivity, the stressed material layer 114 may be used as an etch stop layer during the formation of the via openings 117 and 118. Thereafter, the etch recipe of the anisotropic etch process 124 may be adjusted so as to remove the material of the stressed material/etch stop layer 114 at the bottom of via opening 117 and 118 so as to expose the contact region 112c in the source/drain region 106 and contact region 113c in the gate electrode 109. However, as shown in FIG. 1e, due to the “spotty” nature of the agglomerated nickel silicide regions 112a, via openings 117 may only partially align with the nickel silicide material in contact regions 112c, thereby potentially leading to product defects, as illustrated in FIG. 1f and described below.
FIG. 1f illustrates a further advanced manufacturing stage of the semiconductor 100 depicted in FIG. 1e, wherein a conductive metal layer 119, such as tungsten, copper, silver, and the like, is formed above the interlayer dielectric material layer 115. As shown in FIG. 1f, the conductive metal layer 119 fills the via openings 117 and 118, thereby forming conductive contact elements 117c and 118c, respectively, that provide electrical connection betweens metallization layers (not shown) subsequently formed above the interlayer dielectric material layer 115 and the contact regions 112c and 113c of the transistor element 150. Due to the defects present in the nickel silicide layers 112—i.e., agglomerated nickel silicide regions 112a—the likelihood that a contact “punch through” 120 might occur in the contact regions 112c is substantially increased. As illustrated in FIG. 1f, a contact “punch through” 120 may occur when, during deposition of the conductive metal 119, the conductive contact elements 117c “punch through” the contact regions 112c in the areas between the agglomerated nickel silicide regions 112a, and into the highly doped source/drain regions 106. Due to the contact “punch through” 120 that may be created, a higher resistivity contact may sometimes be created, and the likelihood of contact-to-well current leakage may also increase. Furthermore, the likelihood contact element defects related to “spotty” nickel silicides might occur during device manufacture can significantly increase with more aggressively scaled device technology nodes—such as a change from 45 nm to 32 nm, or even smaller—as it becomes substantially more likely that a given contact element may align at least partially with regions between the agglomerated nickel silicides, thereby leading to “punch through” defects as previously described. As a result, reduced device reliability and/or product yield may be expected.
In view of the quality and reliability concerns cited above, it would therefore be highly desirable to eliminate or at least reduce some of the problems generally associated with forming nickel silicide contact regions in highly sophisticated integrated circuit devices, and more specifically, in PMOS transistor devices. The presently disclosed subject matter is therefore directed to methods for forming silicide regions that may reduce one or more of the problems identified herein.